Manufacturing method for semiconductor devices

ABSTRACT

A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2014-174648 filed onAug. 28, 2014 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a technology of manufacturingsemiconductor devices, such as, for example, a wafer process package andso forth for performing bump bonding.

In assembly of the wafer process package (WPP, and also called WLP:Wafer Level Package), when bonding a solder bump to an electrode that isconfigured by part of a relocation wiring, an oxide film on a surface ofthe electrode is removed.

Thus, in regard to removal of the oxide film when forming the bump (aconductive bump), a description is made, for example, in JapaneseUnexamined Patent Publication No. 2005-44987. In Japanese UnexaminedPatent Publication No. 2005-44987, there is disclosed a technology ofapplying a plurality of times a flux that various components areincluded and compounding ratios of the components are made differentfrom one another onto a UBM (Under Bump Metal) layer of a substrate andremoving an oxide film on a surface of each of the UBM layer and aconductive ball.

In the above-mentioned wafer process package, an electroless Au-platedfilm is formed over the surface of the electrode formed by therelocation wiring in order to prevent a Ni film from being oxidized.However, since the electroless Au-plated film is coarsely formed, oxygenintrudes into the package through a gap in the Au-plated film, thesurface of the Ni film is oxidized and the growth of a Sn—Ni—Cu alloylayer (a reaction layer) is inhibited when forming the solder bump. As aresult, it is feared that defective solder bonding may occur. Inaddition, it is feared that cracks may be generated in flip chipbonding.

SUMMARY

Incidentally, use of Au plating to the electrode is not described inJapanese Unexamined Patent Publication No. 2005-44987.

Other subjects and novel features will become apparent from descriptionof the present specification and the appended drawings.

According to one embodiment of the present invention, there is provideda manufacturing method for semiconductor devices, including the steps of(a) forming an Ni/Au film that includes an Ni film and an Au film formedover the Ni film over a wiring that is coupled to each of a plurality ofelectrode pads formed over a principal surface of a semiconductor waferand arranges each of the electrode pads at a different position, (b)performing reduction treatment on a surface of the Ni/Au film and (c)forming a solder bump over the Ni/Au film.

According to the above-mentioned one embodiment, it is possible toimprove bonding reliability in flip chip bonding of a semiconductordevice.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial plan view illustrating one example of a structure ofmain parts of a semiconductor device manufactured by a manufacturingmethod for semiconductor devices according to an First Embodiment.

FIG. 2 is a partial sectional diagram illustrating one example of thestructure that has been cut along the A-A line in FIG. 1.

FIG. 3 is a flow chart and sectional diagrams illustrating one exampleof a part of the manufacturing method for semiconductor devicesaccording to the First Embodiment.

FIG. 4 is a flow chart and sectional diagrams illustrating one exampleof a part of the manufacturing method for semiconductor devicesaccording to the First Embodiment.

FIG. 5 is a flow chart and sectional diagrams illustrating one exampleof a manufacturing method according to a comparative example.

FIG. 6 is a flow chart and sectional diagrams illustrating one exampleof a part of the manufacturing method for semiconductor devicesaccording to the First Embodiment.

FIG. 7 is a flow chart and a sectional diagram illustrating one exampleof a part of the manufacturing method for semiconductor devicesaccording to the First Embodiment.

FIG. 8 is a flow chart illustrating one example of procedures of bumpmounting pretreatment in the manufacturing method for semiconductordevices according to the First Embodiment.

FIG. 9 is a treatment condition chart illustrating one example of thebump mounting pretreatment illustrated in FIG. 8.

FIG. 10 is a sectional diagram illustrating one example of anadvantageous effect brought about by the bump mounting pretreatment inthe manufacturing method for semiconductor devices according to theFirst Embodiment.

FIG. 11 is a flow chart illustrating one example of procedures of bumpmounting pretreatment in a manufacturing method for semiconductordevices according to an Second Embodiment.

DETAILED DESCRIPTION

In the following embodiments, description on the same or similar partsis not repeated in principle unless otherwise necessary.

Further, although, in the following embodiments, description will bemade by dividing into a plurality of sections or embodiments whennecessary for the convenience sake, these are not unrelated to eachanother and these are related to each other such that one covers some orall of modified examples, details, supplemental explanation and so forthof the other unless otherwise clearly stated.

In addition, in the following embodiments, in a case where the number ofconstitutional elements and so forth (the number of units, a numericalvalue, an amount, a range and so forth are included) is referred to, itis not limited to the specific number, and may be at least and/or notmore than the specific number unless otherwise clearly stated and unlessotherwise definitely limited to the specific number in principle.

In addition, in the following embodiments, it goes without saying thatthe constitutional element (an element step and so forth are alsoincluded) is not necessarily unavoidable unless otherwise clearly statedand unless otherwise thought to be clearly unavoidable in principle.

In addition, in the following embodiments, it goes without saying thatwhen saying that “it is included from A”, “it includes A”, “it has A”,“it includes A” and so forth in regard to the constitutional element andso forth, they do not exclude elements other than the above unlessotherwise clearly stated, in particular, that it means that elementalone. Likewise, in the following embodiments, when the shapes of theconstitutional elements and so forth, a positional relationship amongthem and so forth are referred to, the ones that are substantiallyapproximate or similar to the shapes and so forth will be includedunless otherwise clearly stated and unless otherwise clearly thoughtthat it is not so in principle. The same also applies to theabove-mentioned numerical value and range.

In the following, the embodiments of the present invention will bedescribed in detail on the basis of the drawings. Incidentally, in allof the drawings depicted in order to describe the embodiments, the samenumerals are assigned to members having the same functions andrepetitive description thereof is omitted. In addition, for easyunderstanding of the drawings, there are cases where hatching is appliedeven to a plan view.

First Embodiment

FIG. 1 is a partial plan view illustrating one example of a structure ofmain parts of a semiconductor device manufactured by a manufacturingmethod for semiconductor devices according to an First Embodiment, andFIG. 2 is a partial sectional diagram illustrating one example of thestructure that has been cut along the A-A line in FIG. 1.

<Semiconductor Device>

The semiconductor device manufactured by the manufacturing methodaccording to the First Embodiment and illustrated in FIG. 1 is a waferprocess package 5 and is the semiconductor package of a small size thatis almost the same as the size of a chip.

A configuration of the wafer process package 5 manufactured by themanufacturing method according to the First Embodiment will be describedby using FIG. 1 and FIG. 2. The wafer process package 5 includes asemiconductor chip 2 that includes a principal surface 2 b, a backsurface 2 c that is opposite to the principal surface 2 b, a pluralityof electrode pads formed over the principal surface 2 b, a relocationwiring (a wiring) 2 e that is coupled to each of the plurality ofelectrode pads 2 a and arranges each of the plurality of electrode pads2 a at a different position and a polyimide layer 2 f that is aninsulating film formed over the relocation wiring 2 e.

Further, the wafer process package 5 includes a plurality of solderbumps (projected electrodes) 3 each of which is bonded to an Au (gold)film 2 k that is formed over a partial upper part of the relocationwiring 2 e and the plurality of solder bumps 3 serve as externalterminals of the wafer process package 5.

That is, in the semiconductor chip 2 that the wafer process package 5includes, the plurality of electrode pads 2 a that are provided over theprincipal surface 2 b of the semiconductor chip 2 and the solder bumps 3that are provided over the relocation wirings 2 e via the Au films 2 kare electrically coupled together via the relocation wirings 2 e.

Thereby, an installation pitch of the plurality of electrode pads 2 aprovided over the principal surface 2 b of the semiconductor chip 2 iswidened by the relocation wirings 2 e and each of the plurality ofsolder bumps 3 is bonded to a new electrode (a region of the Au film 2k) provided over each relocation wiring 2 e.

Incidentally, the relocation wiring 2 e is also called a rewiring.

In addition, each of the plurality of electrode pads 2 a is made of, forexample, Al (aluminum) and so forth. Then, the relocation wiring 2 e isa wiring that includes, for example, Cu (copper) as a principalcomponent, an Ni (nickel) film 2 n is formed over its upper layer and alaminated film 2 h that includes a Cr (chromium) film serving as abarrier layer and a Cu film serving as a seed layer is formed over itslower layer. In the present embodiment, for simplicity of description,the laminated film is indicated as the seed layer 2 h. Therefore, therelocation wiring 2 e may be also regarded as the wiring having astructure that includes the seed layer 2 h, a Cu film 2 j and the Nifilm 2 n and, in this case, the seed layer 2 h, the Cu film 2 i and theNi film 2 n are arranged in order from the lower layer side toward theupper layer side.

Then, in the relocation wiring 2 e, the seed layer 2 h formed over itslower layer is bonded with the electrode pad 2 a and the Ni film 2 nformed over its upper layer is bonded with the solder bump 3 via the Aufilm 2 k.

Incidentally, each of the plurality of solder bumps 3 is arranged ineach of a plurality of openings 2 m in the polyimide layers 2 frespectively formed over the relocation wirings 2 e. That is, the Aufilm 2 k is formed in each of the plurality of openings 2 m in thepolyimide layers 2 f formed over the relocation wirings 2 e. When havingan eye on a region of the opening 2 m, a Ni/Au film that includes the Nifilm 2 n and the Au film 2 k formed over the Ni film 2 n is formed overthe relocation wiring 2 e and the Au film 2 k is exposed into theopening 2 m.

In addition, the Au film 2 k that is plated with Au is formed over theNi film 2 n for the purpose of preventing the Ni film 2 n from beingoxidized and of ensuring solder wettability (improving bonding propertyof the solder bump 3).

Then, as illustrated in FIG. 2, a plurality of wiring patterns 2 p areformed in a wiring layer that is the same as the layer that theelectrode pads 2 a of the semiconductor ship 2 are provided.

In addition, in the wafer process package 5, the solder bumps 3 thatserve as the plurality of external terminals are arrayed in the form ofa grid as illustrated in FIG. 1 on the principal surface 2 b side of thesemiconductor chip 2 and the arrangement of the solder bumps 3 is thesame as that of BGA (Ball Grid Array) in external appearance.

In addition, as described above, in the wafer process package 5illustrated in FIG. 2, the relocation wiring 2 e is further coupled tothe electrode pad 2 a that has been formed over the principal surface 2b of the semiconductor chip 2 and the solder bump 3 is coupled to therelocation wiring 2 e via the Au film 2 k. That is, the wafer processpackage 5 is of the type that the arrangement pitch of the electrodepads 2 a has been narrowed. Since pitch narrowing makes it difficult tomount the solder bump 3 that is the external terminal directly onto theelectrode pad 2 a, the solder bump 3 is coupled to the relocation wiring2 e by widening the pitch by the relocation wiring 2 e so as to allowmounting of the solder bump 3.

Thereby, it becomes possible to arrange the plurality of solder bumps 3in the form of a grid.

<Manufacturing Method for Semiconductor Devices>

Next, a manufacturing method for semiconductor devices according to thepresent embodiment will be described. Each of FIG. 3 and FIG. 4 is aflow chart and sectional diagrams illustrating one example of a part ofthe manufacturing method for semiconductor devices according to theFirst Embodiment.

First, “Polyimide Layer Patterning” illustrated in FIG. 3 is performed.In the polyimide layer patterning, a polyimide layer 2 d is formed overa principal surface 1 a of a semiconductor wafer 1, and then an upperpart of the electrode pad 2 a is opened by patterning. Thereby, itbecomes possible to expose the electrode pad 2 a into an opening 2 j inthe polyimide layer 2 d. Incidentally, the electrode pad 2 a is made of,for example, Al and so forth.

After the polyimide layer patterning has been completed, “Seed LayerSputtering” illustrated in FIG. 3 is performed. In the seed layersputtering, the seed layer 2 h is formed (deposited) by sputtering overthe polyimide layer 2 d and the electrode pad 2 a. Thereby, theelectrode pad 2 a that is made of Al and so forth and the seed layer 2 hare electrically coupled together. In formation of the seed layer 2 h,first, the Cr film is formed as the barrier layer and the Cu film isformed over the Cr film as the seed layer. In the present embodiment,for simplicity of description, the laminated film that includes the Crfilm and the Cu film is noted as the seed layer 2 h. Incidentally, inthe seed layer 2 h, the barrier layer may be configured by either of theabove-mentioned Cr film and a film made of, for example, titanium and soforth.

After the seed layer sputtering has been completed, “Resist Patterning”illustrated in FIG. 3 is performed. In the resist patterning, a portionfor the relocation wiring 2 e to be formed in a later process is left asit is and a region other than that portion is covered with a resist 2 g.

After the resist patterning has been completed, “RelocationWiring-Formation by Cu/Ni Plating” illustrated in FIG. 3 is performed.In the relocation wiring—formation by Cu/Ni plating, first, the Cu filmis formed by electroplating and then the Ni film is formed byelectroplating.

Describing in detail, first, the Cu film 2 i formed by electroplatingover the seed layer 2 h in a region surrounded by the resist 2 g.Thereby, the relocation wiring (the Cu film 2 1 ) 2 e that includes Cuas the principal component is formed over the seed layer 2 h. Then, theNi film 2 n is formed over the surface of the relocation wiring 2 e byelectroplating. Thereby, the seed layer 2 h, the relocation wiring 2 e(the Cu film 2 i) and the Ni film 2 n are formed.

After the relocation wiring—formation by Cu/Ni plating has beencompleted, “Resist Removal/Wet Etching” illustrated in FIG. 4 isperformed. In the resist removal/wet etching, the resist 2 g thatsurrounds the relocation wiring 2 e is removed by the wet-etching.

After the resist removal/wet etching has been completed, “PolyimideLayer Patterning” illustrated in FIG. 4 is performed. In the polyimidelayer patterning, the polyimide layer 2 f is formed over the relocationwiring 2 e and the partial upper part of the relocation wiring 2 e isopened by patterning. Thereby, the opening 2 m is formed in thepolyimide layer 2 f and part of the Ni film 2 n formed over therelocation wiring 2 e is exposed into the opening 2 m. That is, a statewhere the Ni film 2 n that configures the upper layer film of therelocation wiring 2 e is exposed into the opening 2 m is obtained.

After the polyimide layer patterning has been completed, “Formation byElectroless Au Plating” illustrated in FIG. 4 is performed. In theformation by electroless Au plating, the Au film 2 k is formed over theNi film 2 n that is exposed into the opening 2 m in the polyimide layer2 f by electroless Au plating. Thereby, the Au film 2 k (the Ni/Au film)formed over the relocation wiring 2 e is exposed into the opening 2 m inthe polyimide layer 2 f.

Incidentally, the Au film 2 k is formed for the purpose of preventingthe Ni film 2 n that configures the lower layer from being oxidized andof ensuring solder wettability (improving the bonding property of thesolder bump 3).

In addition, in the First Embodiment, the Au film 2 k is formed byelectroless plating. Since use of electroless plating eliminatesformation of a wiring for electric field in comparison withelectroplating, it is possible to promote a reduction in cost forformation of the Au film 2 k.

Incidentally, in the First Embodiment, as one example of the electrolessplating, displacement plating is adopted. The displacement plating is ofthe type that metal ions in a solution are precipitated as a metal byutilizing a difference in ionization tendency between metals, and it ispossible to promote a reduction in cost as described above by adoptingthe replacement plating.

Here, disadvantages which would occur caused by Au plating performed onthe relocation wiring 2 e will be described. FIG. 5 is a flow chart andsectional diagrams illustrating one example of a manufacturing methodaccording to a comparative example that has been examined in comparisonwith the present embodiment.

As illustrated in “Formation by Au Plating” in FIG. 5, the Au film 2 kthat is an Au-plated film is formed by electroless Au plating over aconductor 2 q formed by Ni plating. In this case, in formation byelecrroless Au plating, in particular, by replacement Au plating,elution of abase material metal (Ni) occurs, and therefore formation ofa “coarse” part on the base material metal (Ni) is unavoidable and Nibecomes liable to be oxidized.

That is, as illustrated in “Oxygen Intrusion” in FIG. 5, oxygen intrudesinto the conductor 2 q through the gap in the Au film 2 k and a surfaceof the Ni film over the conductor 2 q is oxidized (a Ni-oxidized part Pin FIG. 5) as illustrated in “Ni Oxidization” in FIG. 5.

Then, when the solder bump 3 is formed over (bonded to) the Au film 2 kin a later process, growth of a Sn—Ni—Cu alloy layer (a reaction layer)is inhibited, which consequently leads to a failure in solder bonding.

In addition, cracks are generated when bonding the semiconductor deviceto a flip chip via the solder bump 3.

Accordingly, in the First Embodiment, before the solder bump 3 ismounted over (formed over or bonded to) the Au film 2 k (the Ni/Aufilm), an oxide and/or an oxide film formed over the Au film 2 k isremoved by performing later described bump mounting pretreatment(reduction treatment).

Next, after the formation by electroless Au plating has been completed,“Probe Inspection” illustrated in FIG. 6 is performed. FIG. 6 is a flowchart and sectional diagrams illustrating one example of a part of themanufacturing method for semiconductor devices according to the FirstEmbodiment, and FIG. 7 is a flow chart and a sectional diagramillustrating one example of a part of the manufacturing method forsemiconductor devices according to the First Embodiment.

In the probe inspection, a probe 4 is brought into contact with the Aufilm 2 k over the relocation wiring 2 e and electric inspection isperformed in this state.

After the probe inspection has been performed, “Back Grinding”illustrated in FIG. 6 is performed. In the back grinding, aback surface1 b that is opposite to the principal surface 1 a of the semiconductorwafer 1 is ground to reduce the thickness of the semiconductor wafer 1.That is, before forming the solder bump 3 over the Au film 2 k, the backsurface 1 b of the semiconductor wafer 1 is ground to thin thesemiconductor wafer 1.

Incidentally, when the back grinding is performed before forming thesolder bump 3, since the solder bump 3 is not yet attached to theprincipal surface 1 a of the semiconductor wafer 1, and thus theprincipal surface 1 a of the semiconductor wafer 1 is in a flat stateand the principal surface 1 a side serves as the side that holds thesemiconductor wafer 1 in the back grinding, the semiconductor wafer 1 isheld and ground with ease when the principal surface 1 a is made flat.Therefore, it is also possible to increase grinding accuracy.

Further, it is easier to stick and remove a not illustrated tape forback grinding (hereinafter, also referred to as a BG tape) in a casewhere the solder bump 3 is not attached to the principal surface 1 a ofthe semiconductor wafer 1 than other cases. That is, it is possible tofacilitate scraping of the semiconductor wafer 1 and to increase thegrinding accuracy by performing the back grinding before forming thesolder bump 3. Further, it is possible to facilitate sticking andremoval of the tape for back grinding.

After the back grinding has been completed, “Solder Bump Mounting”illustrated in FIG. 7 is performed. In that occasion, in the FirstEmbodiment, after the back grinding has been performed and before thesolder bump mounting is performed, reduction treatment is performed onthe surface of the Au film 2 k (the Ni/Au film) over the relocationwiring 2 e. Incidentally, hereinafter, the reduction treatment will bealso referred to as bump mounting pretreatment or flux reflow solderingpretreatment.

Here, the reduction treatment (the bump mounting pretreatment or theflux reflow soldering pretreatment) of the First Embodiment will bedescribed. FIG. 8 is a flow chart illustrating one example of proceduresof the bump mounting pretreatment in the manufacturing method forsemiconductor devices according to the First Embodiment, FIG. 9 is atreatment condition chart illustrating one example of the bump mountingpretreatment illustrated in FIG. 8, and FIG. 10 is a sectional diagramillustrating one example of an advantageous effect brought about by thebump mounting pretreatment in the manufacturing method for semiconductordevices according to the First Embodiment.

As illustrated in FIG. 8, the reduction treatment (the bump mountingpretreatment) includes three processes of flux application (applicationof a flux constituent material), reflow soldering and cleaning.

First, the flux application will be described.

Incidentally, as the flux constituent material used in the reductiontreatment, the material that is the same as the flux material to beapplied to the Au film 2 k after the reduction treatment has beenperformed and before the solder bump 3 is formed (mounted) is used.

By using the material that is the same as the flux material to beapplied to the Au film 2 k after the reduction treatment has beenperformed as the flux constituent material used in the reductiontreatment in the First Embodiment as described above, it is possible toshape a device for use in flux application. In addition, it is alsopossible to share the flux material itself. Further, it is possible toperform the reduction treatment without changing a method for fluxtreatment by using the same flux material.

Here, the flux constituent material used in the reduction treatment willbe described. The flux constituent material is configured by, forexample, rosin, a solvent, a thixotropic agent, a halogenated activator,an auxiliary activator, an organic acid and so forth. That is, the fluxconstituent material is a rosin-based flux.

However, as the flux constituent material, a water-soluble flux thatdissolves in water may be used, not limited to the rosin-based flux, andin this case, the same water-soluble flux is used as the flux materialto be applied to the Au film 2 k after the reduction treatment has beenperformed and before the solder bump 3 is formed (mounted).

Incidentally, the rosin-based flux has such a characteristic that itdoes not get dry easily. Further, a margin is large in wetting up of thesolder. Therefore, it is also possible to cope with a product of highquality such as an on-vehicle semiconductor device (the wafer processpackage 5) and so forth by using the rosin-based flux.

On the other hand, since the water-soluble flux is low in viscosity, itis possible to apply the water-soluble flux also by a spin coatingmethod. Therefore, it is possible to promote a reduction in cost forcleaning treatment by using the water-soluble flux.

Then, the flux constituent material is applied onto the surface of theAu film 2 k over the relocation wiring 2 e by the flux application inthe reduction treatment. In the flux application, the flux is applied toa desired portion by a ball mounting machine as indicated by “FluxApplication” in FIG. 9.

For example, a mask that is opened to a position on the Au film 2 kformed over the relocation wiring 2 e is used to apply the flux to aportion (the Au film 2 k) to which the flux is to be applied through theopening so opened in the mask. Since it is difficult to remove therosin-based flux and disadvantages such as corrosion, leakage and soforth would possibly occur when the flux is adhered to a portion otherthan the Au film 2 k, it is preferable to apply the flux with care suchthat the flux is not adhered to the portion other than the desirableportion.

On the other hand, the water-soluble flux is easily soluble in water andis removed with ease. Therefore, when applying the water-soluble flux,it is possible to apply the flux highly efficiently by applying the fluxto the entire surface of the semiconductor wafer 1 by the spin-coatingmethod.

After the flux application in the reduction treatment has beencompleted, “Reflow Soldering” in “Reduction Treatment” (“Bump MountingPretreatment”) in FIG. 8 is performed. In the reflow soldering, asindicated in “Reflow Soldering (Temperature Rising)” in FIG. 9, thetemperature is raised in a reflow furnace under reflow solderingconditions. For example, the flux is heated for several minutes at atemperature from about 200° C. to about 300° C. that are solder meltingtemperatures (solder activation temperatures).

Thereby, the activator in the flux constituent material is heated tomake it possible to remove the oxide and/or the oxide film over thesurface of the Au film 2 k formed over the relocation wiring 2 e.

After the reflow soldering in the reduction treatment has beencompleted, “Cleaning” in “Reduction Treatment (Bump MountingPretreatment)” in FIG. 8 is performed. In the cleaning, as indicated by“Cleaning” in FIG. 9, the flux is removed under the same conditions asthose in post-cleaning of reflow soldering that comes after the solderbump mounting.

Specifically, the flux material is washed out by spraying a surfactantto the semiconductor wafer 1 while rotating the semiconductor wafer 1 byspin cleaning. However, the cleaning is not limited to spin cleaning andmay be of the type that the semiconductor wafer 1 is cleaned in a stateof being soaked in a liquid tank that contains the surfactant.

Then, after the cleaning with the surfactant has been completed, it ispossible to wash out the flux material by spraying pure water (spincleaning) to the semiconductor wafer 1. However, also the cleaning withpure water is not limited to the spin cleaning and the flux material maybe washed out by cleaning the semiconductor wafer 1 in a state of beingsoaked in the liquid tank.

Form the above, the reduction treatment of the manufacturing methodaccording to the First Embodiment is completed.

Thereby, it is possible to remove the oxide and/or the oxide film formedover the surface of the Au film 2 k formed over the relocation wiring 2e. That is, it is possible to remove the oxide and/or the oxide filmformed over the surface of the Au film 2 k by performing the reductiontreatment (the bump mounting pretreatment) that includes the fluxapplication, the reflow soldering (the temperature rising) and thecleaning on the Au film 2 k.

After the reduction treatment has been completed, flux application thatcomes after the reduction treatment (the bump mounting pretreatment)indicated in FIG. 8 is performed. Here, the flux application that comesafter the reduction treatment is performed on the Au film 2 k over therelocation wiring 2 e that the oxide and/or the oxide film have/has beenremoved by the reduction treatment.

In the flux application that comes after the reduction treatment, theflux is applied to the Au film 2 k over the relocation wiring 2 e byusing the flux material (the flux constituent material) that is the sameas that in the flux treatment performed in the reduction treatment andby the same method.

The rosin-based flux material that is configured by, for example, therosin, the solvent, the thixotropic agent, the halogenated activator,the auxiliary activator, the organic acid and so forth is used, and theflux material is applied to the surface of the Au film 2 k. In thatoccasion, as in the case in the reduction treatment, the flux is appliedto the desired portion by the ball mounting machine.

For example, the mask that is opened to the position on the Au film 2 kformed over the relocation wiring 2 e is used to apply the flux to theportion (the Au film 2 k) to which the flux is to be applied through theopening so opened. Since it is difficult to remove the rosin-based fluxand the disadvantages such as the corrosion, the leakage and so forthwould possibly occur when the flux is adhered to the portion other thanthe Au film 2 k, the flux is applied with care such that the flux is notadhered to the portion other than the desirable portion.

However, in a case where the water-soluble flux has been used in thereduction treatment, the water-soluble flux is also used in the fluxapplication that comes after the reduction treatment.

Incidentally, the flux application that comes after the reductiontreatment is performed for the purpose of temporarily attaching thesolder bump 3 when mounting the solder bump 3 and removing the oxidesand/or the oxide films formed over the surfaces of both of the Au film 2k and the solder bump 3. That is, temporal attachment of the solder bump3 is performed in order to retain the solder bump 3 that has beenarranged over the Au film 2 k for a while until reflow soldering isperformed in a later solder bump mounting process. In addition, theoxide and/or the oxide film over the surface of the solder bump 3 are/isremoved by washing the surface of the solder bump 3 while rotating thesolder bump 3 in reflow soldering.

After the flux application that comes after the reduction treatment hasbeen completed, solder bump mounting is performed. That is, the solderbump 3 is formed over the Au film 2 k over the relocation wiring 2 e. Inthe solder bump mounting, the solder bump 3 is mounted onto each of apredetermined plurality of the Au films 2 k by using the ball mountingmachine.

After the solder bump mounting has been completed, reflow soldering thatcomes after the reduction treatment is performed. In the reflowsoldering, the temperature of the solder bump 3 is raised in the reflowfurnace under the reflow soldering conditions. For example, the solderbump 3 is heated at the temperature from about 200° C. to about 300° C.that are the solder melting temperatures (the solder activationtemperatures).

Thereby, the activator in the flux material is heated to make itpossible to remove the oxide and/or the oxide film formed over thesurface of the Au film 2 k. Further, as mentioned above, it is alsopossible to remove the oxide and/or the oxide film over the surface ofthe solder bump 3 by rotating the solder bump 3.

After the reflow soldering for mounting the solder bump 3 has beencompleted, “Cleaning” that comes after “Reduction Treatment” in FIG. 8is performed. In the cleaning, as one example, the flux material iswashed out by spraying the surfactant to the semiconductor wafer 1 whilerotating the semiconductor wafer 1. However, as in the case in thereduction treatment, cleaning is not limited to spin cleaning and may beof the type that the flux material is washed out by soaking thesemiconductor wafer 1 in the liquid tank that contains the surfactant.

Then, after the semiconductor wafer 1 has been cleaned with thesurfactant, the flux material is washed out by spraying pure water (spincleaning) to the semiconductor wafer 1. However, the flux material maybe washed out by cleaning the semiconductor wafer 1 in a state of beingsoaked in the liquid tank also in cleaning with pure water, not limitedto spin cleaning.

From the above, the solder bump mounting illustrated in FIG. 7 iscompleted.

After the solder bump mounting has been completed, “Dicing” illustratedin FIG. 7 is performed to cut out the respective semiconductor chips 2from the semiconductor wafer 1.

Then, fragmentation is performed by dicing and assembling of the waferprocess package 5 illustrated in FIG. 1 is completed.

According to the manufacturing method for the semiconductor deviceaccording to the First Embodiment, before the solder bump 3 is bonded to(formed over) the Au film 2 k over the relocation wiring 2 e, it ispossible to remove the oxide and/or the oxide film formed over thesurface of the Au film 2 k by performing the reduction treatment (thebump mounting pretreatment), the flux application, the reflow soldering(temperature rising), the cleaning and so forth on the surface of the Aufilm 2 k.

Thereby, it becomes possible to promote the growth of a solder-bondedinterface (the Sn—Ni—Cu alloy layer (the reaction layer 7 in FIG. 10))when the solder bump is to be bonded to the surface of the Au film 2 kand it becomes possible to suppress generation of cracks which wouldgenerate in flip chip bonding.

Here, FIG. 10 is a diagram illustrating one example of a structure ofthe bonded interface of the solder bump 3 in a case where the waferprocess package 5 that is illustrated in FIG. 1 and on which thereduction treatment has been performed has been flip-chip mounted onto amounted substrate and so forth, illustrating a state where a reactionlayer 7 that is an Sn—Ni—Cu alloy layer formed between an Ni layer 8 anda solder layer 6 grows with continuity and thereby the growth ispromoted and the reaction layer 7 is formed thick.

Therefore, it is possible to suppress generation of the cracks inflip-chip bonding.

As a result, it is possible to improve the bonding reliability inflip-chip bonding of the wafer process package 5.

Second Embodiment

FIG. 11 is a flow chart illustrating one example of procedures of bumpmounting pretreatment in a manufacturing method for semiconductordevices according to an Second Embodiment.

In the Second Embodiment, as the bump mounting pretreatment (thereduction treatment), “Acid Cleaning” is performed as indicated in FIG.11. That is, cleaning (acid cleaning) using an acid is performed for thepurposes of removing the oxide and/or the oxide film formed over thesurface of the Au film 2 k that has been formed over the relocationwiring 2 e.

Specifically, after the probe inspection illustrated in FIG. 6 has beenperformed, the back grinding is not performed and the solder bumpmounting illustrated in FIG. 7 is performed. That is, in the SecondEmbodiment, before performing the back grinding, the acid cleaningillustrated in FIG. 11 is performed. Then, the back grinding isperformed after the acid cleaning that is the reduction treatment andthe solder bump mounting have been completed.

In the acid cleaning, although it is preferable to perform the cleaningby using an acid such as, for example, hydrochloric acid (HCl) ,sulfuric acid (H₂SO₄) and so forth, the acid to be used is not limitedto these acids. Then, the semiconductor wafer 1 that has been subjectedto the probe inspection is soaked in the liquid tank and so forth that asolution (a liquid medicine) such as, for example, hydrochloric acid,sulfuric acid and so forth is contained and then is immersed in arinsing tank that pure water and so forth are contained to wash out theliquid medicine.

Here, since hydrochloric acid, sulfuric acid and so forth are handled ascleaning solutions, it is more preferable to adopt a cleaning methodthat the semiconductor wafer 1 is immersed in the liquid tank and soforth than adoption of the spin coating method and adoption of theabove-mentioned cleaning method makes it possible for a worker to dowork more safely.

Form the above, the acid cleaning is completed.

Thereby, it is possible to clean the surface of the Au film 2 k over therelocation wiring 2 e and it is possible to remove the oxide and/or theoxide film formed over the surface of the Au film 2 k.

After the acid cleaning has been completed, “Flux Application” thatcomes after “Bump Mounting Pretreatment (Reduction Treatment)”illustrated in FIG. 11 is performed. Here, similarly to the FirstEmbodiment, “Flux Application” is performed on the Au film 2 k over therelocation wiring 2 e from which the oxide and/or the oxide filmhave/has been removed by the acid cleaning (the reduction treatment).

In the flux application, the flux is applied to the Au film 2 k over therelocation wiring 2 e by using the flux material (the flux constituentmaterial) that is the same as that in the First Embodiment and by usingthe same method as that in the First Embodiment.

The rosin-based flux material that is configured by, for example, therosin, the solvent, the thixotropic agent, the halogenated activator,the auxiliary activator, the organic acid and so forth is used, and theflux material is applied to the surface of the Au film 2 k. In thatoccasion, similarly to the First Embodiment, the flux is applied to thedesired portion, for example, by the ball mounting machine.

That is, also in the Second Embodiment, the mask that is opened to theposition on the Au film 2 k formed over the relocation wiring 2 e isused to apply the flux to the portion (the Au film 2 k) to which theflux is to be applied through the opening so opened. Since it isdifficult to remove the rosin-based flux and the disadvantages such asthe corrosion, the leakage and so forth would possibly occur when theflux is adhered to the portion other than the Au film 2 k, the flux isapplied with care such that the flux is not adhered to the portion otherthan the desirable portion.

Incidentally, the flux is applied for the purpose of temporarilyattaching the solder bump 3 when mounting the solder bump 3 and removingthe oxides and/or the oxide films formed over the surfaces of both ofthe Au film 2 k and the solder bump 3. That is, temporal attachment ofthe solder bump 3 is performed in order to retain the solder bump 3 thathas been arranged over the Au film 2 k for a while until reflowsoldering is performed in the later solder bump mounting process. Inaddition, the oxide and/or the oxide film formed over the surface of thesolder bump 3 are/is removed by washing the surface of the solder bump 3while rotating the solder bump 3 in reflow soldering.

After the flux application has been completed, “Solder Bump Mounting”indicated in FIG. 11 is performed. That is, the solder bump 3 is formedover the Au film 26 k that has been formed over the relocation wiring 2e. In the solder bump mounting, the solder bump 3 is mounted onto eachof the predetermined plurality of Au films 2 k by using the ballmounting machine, similarly to the First Embodiment.

After the solder bump mounting has been completed, “Reflow Soldering”indicated in FIG. 11 is performed. In the reflow soldering, thetemperature of the solder bump 3 is raised in the reflow furnace underthe reflow soldering conditions similarly to the First Embodiment. Forexample, the solder bump 3 is heated at the temperature from about 200°C. to about 300° C. that are the solder melting temperatures (the solderactivation temperatures).

Thereby, the activator in the flux material is heated to make itpossible to remove the oxide and/or the oxide film formed over thesurface of the Au film 2 k. Further, as mentioned above, it is alsopossible to remove the oxide and/or the oxide film formed over thesurface of the solder bump 3 by rotating the solder bump 3.

After the reflow soldering indicated in FIG. 11 has been completed,“Cleaning” is performed. In the cleaning, as one example, similarly tothe First Embodiment, the flux material is washed out by spraying thesurfactant to the semiconductor wafer 1 while rotating the semiconductorwafer 1 by spin cleaning. However, the cleaning is not limited to thespin cleaning and may be of the type that the semiconductor wafer 1 iscleaned by soaking it in the liquid tank that contains the surfactant.

Then, after the cleaning with the surfactant has been completed, theflux material is washed out by spraying pure water (spin cleaning) tothe semiconductor wafer 1 similarly to the First Embodiment. However,also cleaning with pure water is not limited to spin cleaning and may beof the type that the flux material is washed out by cleaning thesemiconductor wafer 1 in a state of being soaked in the tank.

From the above, the solder bump mounting indicated in FIG. 11 iscompleted.

After the solder bump mounting has been completed, “Back Grinding”indicated in FIG. 11 is performed in the Second Embodiment. That is,after the solder bump 3 has been formed (mounted) over the Au film 2 kformed over the relocation wiring 2 e, the back surface 1 b that isopposite to the principal surface 1 a of the semiconductor wafer 1 isground.

Here, in the Second Embodiment, the reason why the back grinding isperformed after the acid cleaning (the bump mounting pretreatment) thatis the reduction treatment and the solder bump mounting have beencompleted will be described.

That is, each of the processes illustrated in FIG. 3 and FIG. 4 is apre-process in the semiconductor manufacturing process and since thesemiconductor wafer 1 that has been back-ground is thin and hence hassuch a disadvantage that it readily cracks in transportation, it isregarded to be difficult for each manufacturing equipment used in eachpreprocess to handle the semiconductor wafer 1 so back-ground. Further,although in the acid cleaning, the acids such as hydrochloric acid,sulfuric acid and so forth are used, since in the pre-process,hydrochloric acid, sulfuric acid and so forth are used in treatment incomparison with a post-process and an environment that the acids arehandled with ease is well arranged.

Thus, in the Second Embodiment, the acid cleaning (the bump mountingpretreatment) that is the reduction treatment is performed in thepre-process before performing the back grinding and the back grinding isperformed in the post-process after the solder bump mounting has beencompleted.

In a case where the back grinding is performed after completion of thesolder bump mounting, it is unavoidable to hold a bump mounting surfaceof the semiconductor wafer 1, and therefore the BG tape that is madethick in adhesion layer that allows absorption of the height of the bumpis stuck to the bump mounting surface and the back grinding is performedin a state where each solder bump 3 is being protected by the BG tapethe adhesion layer of which is made thick.

That is, the BG tape the adhesion layer of which is made thick is stuckto the bump mounting surface (the principal surface la) of thesemiconductor wafer 1 so as to absorb the height of the bump with thethickness of the adhesion layer and the back grinding is performed in astate of holding the bump mounting surface.

From the above, when the acid cleaning is to be performed, it ispossible to handle the semiconductor wafer 1 even in the pre-processbecause the semiconductor wafer 1 is not yet back-ground and thethickness thereof is still in a thick state. In addition, since theenvironment that hydrochloric acid, sulfuric acid and so forth are usedis well arranged, it is possible to perform the acid cleaning by usingexisting equipment.

In addition, it is possible to perform the back grinding even in thepost-process by using the BG tape the adhesion layer of which is madethick.

However, although the acid cleaning may be performed in thepost-process, it is more preferable to perform the acid cleaning in thepre-process for the above-mentioned reasons.

Thereby, the back grinding of the semiconductor wafer 1 is completed.

After the back grinding has been completed, “Dicing” illustrated in FIG.7 is performed to cut out the respective semiconductor chips 2 from thesemiconductor wafer 1.

Then, segmentation is performed by the dicing and assembly of the waferprocess package 5 illustrated in FIG. 1 is completed.

According to the manufacturing method for semiconductor devicesaccording to the Second Embodiment, before the solder bump 3 is bondedto (formed over) the Au film 2 k formed over the relocation wiring 2 e,it is possible to remove the oxide and/or the oxide film formed over thesurface of the Au film 2 k by performing the acid cleaning on thesurface of the Au film 2 k as the reduction treatment (the bump mountingpretreatment).

Thereby, similarly to the First Embodiment, it is possible to promotethe growth of the solder bonded interface (the Sn—Ni—Cu alloy layer (thereaction layer 7 illustrated in FIG. 10)) when the solder bump bondingis performed and it is possible to suppress generation of cracks inflip-chip bonding.

As a result, it is possible to improve the bonding reliability inflip-chip bonding of the wafer process package 5.

In addition, in the Second Embodiment, as the reduction treatment, onlythe acid cleaning is performed and the reflow soldering is notperformed. Therefore, it is possible to reduce exertion of heat stressto the semiconductor wafer 1 caused by heating for reflow soldering andit is possible to suppress a failure caused by the heat stress such as afault that the cracks grow, for example, in flip-chip mounting of thewafer process package 5.

Further, since the acid cleaning in the Second Embodiment is simple incleaning process in comparison with other cleaning methods, it ispossible to promote a reduction in cost for cleaning.

MODIFIED EXAMPLES

Although, in the foregoing, the invention made by the inventors andothers of the present invention has been specifically described on thebasis of the preferred embodiments, it goes without saying that thepresent invention is not limited to the aforementioned embodiments andmaybe modified in a variety of ways within the scope not deviating fromthe gist of the present invention.

Modified Example 1

Although in the above-mentioned embodiments 1 and 2, a case where thesemiconductor device is the wafer process package has been described,the semiconductor device may be another semiconductor package as long asit is the package that includes the relocation wiring and the Ni/Au filmformed over the relocation wiring.

Modified Example 2

Further, application of modified examples is possible by mutuallycombining them within the scope not deviating from the gist of thetechnical idea described in the embodiments.

1-12. (canceled)
 13. A method for manufacturing a semiconductor device,comprising: (a) providing a semiconductor substrate having a multilayerwiring and an electrode pad formed at an uppermost layer of themultilayer wiring; (b) after (a), forming a rewiring electricallycoupled to the electrode pad; (c) after (b), forming a first metal filmover the rewiring; (d) after (c), forming a second metal film over thefirst metal film; (e) after (d), performing a reduction treatment on asurface of the second metal film; and (f) after (e), forming a bump overthe second metal film.
 14. The method for manufacturing a semiconductordevice according to claim 13, wherein the first metal film is a Ni film.15. The method for manufacturing a semiconductor device according toclaim 14, wherein the second metal film is an Au film.
 16. The methodfor manufacturing a semiconductor device according to claim 13, whereinthe bump is an Sn bump.
 17. The method for manufacturing a semiconductordevice according to claim 14, wherein (e) comprises: (e1) applying aflux constituent material; (e2) after (e1), performing reflow soldering;and (e3) after (e2), performing cleaning.
 18. The method formanufacturing a semiconductor device according to claim 17, wherein theflux constituent material is a same material as that of a flux materialthat is applied to the second metal film after the reduction treatmenthas been performed and before the bump is formed.
 19. The method formanufacturing a semiconductor device according to claim 18, whereinbefore (f), a back surface that is opposite to a principal surface ofthe semiconductor substrate is ground.
 20. The method for manufacturinga semiconductor device according to claim 13, further comprising:grinding a back surface of the semiconductor substrate, the back surfacebeing opposite to a principal surface of the semiconductor substrate,the multilayer wiring being formed over the principal surface.
 21. Themethod for manufacturing a semiconductor device according to claim 13,wherein the reduction treatment comprises acid cleaning.
 22. The methodfor manufacturing a semiconductor device according to claim 13, whereinthe forming the second metal film in (d) includes electroless plating.23. A method for manufacturing a semiconductor device, comprising:forming a first metal film over a rewiring on a semiconductor substrate,the semiconductor substrate having a multilayer wiring and an electrodepad formed at an upper layer of the multilayer wiring, the rewiringbeing electrically connected to the electrode pad; forming a secondmetal film over the first metal film; performing a reduction treatmenton a surface of the second metal film; and forming a bump over thesecond metal film after the reduction treatment.
 24. The method of claim23, wherein the first metal film comprises Ni.
 25. The method of claim23, wherein the second metal film comprises Au.
 26. The method of claim23, wherein the bump comprises Sn.
 27. The method of claim 23, whereinthe performing the reduction treatment comprises applying a fluxconstituent material followed by reflow soldering and cleaning.